1. Field of the Invention
The present invention relates to logic gates having input and output signals and, in particular, to logic gates with glitch-free output signals.
2. Description of the Related Art
Logic gates are used in a wide variety of systems. Typical logic gates include AND, OR, NAND, and NOR logic gates. In a mixed system having both synchronous and asynchronous components, gates are considered to be asynchronous elements. Unfortunately, logic gates having two or more inputs, such as AND and OR gates, are prone to glitches.
Referring now to FIGS. 1A-C, there is shown an input signal timing diagram 100, and OR and AND logic gates 120, 140 and accompanying output signal timing diagrams 130, 150, respectively, illustrating the OR gate and AND gate glitch problems encountered by prior art logic gates. As shown in input signal timing diagram 100, a synchronous clock signal CLK is used in the system employing OR and AND gates 120, 140. Input signals A and B appear in the system, and ideally transition only at the moment of the positive (upward) edge transition of the clock signal CLK. However, in practical implementations, there is typically a slight skew between the two input signals undergoing simultaneous transitions. When the two input signals are simultaneously transitioning in different directions, this can lead to glitches in the output. In the present application, two signals are considered to transition simultaneously, even if there is some skew therebetween, as long as each signal transitions due to the same clock signal transition.
As illustrated in FIG. 1B, OR gate 120 has input signals A.sub.1, B.sub.1, and output signal C.sub.1. At a positive edge of the clock signal CLK A.sub.1 transitions up and B.sub.1 transitions down. However, there is a slight A.sub.1 /B.sub.1 skew therebetween, causing a momentary glitch 135 to be produced in output C.sub.1.
Similarly, as illustrated in FIG. 1C, AND gate 140 has input signals A.sub.2, B.sub.2, and output signal C.sub.2. At a positive edge of the clock signal CLK A.sub.2, transitions up and B.sub.2 transitions down. However, there is a slight A.sub.2 /B.sub.2 skew therebetween, causing a momentary glitch 155 to be produced in output C.sub.2. If the outputs of the logic gates 120, 140 are not latched, output glitches 135, 155 can propagate throughout the system and cause potential failures.